| Yutaka Ishikawa Chief Massively Parallel Software Lab. Real World Computing Partnership |
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| Yutaka Ishikawa Chief Massively Parallel Software Lab. Real World Computing Partnership |
I would like to explain briefly the research results regarding massively parallel systems and optical systems for the first five-year period of the RWC Project.
We have been conducting research and development on massively parallel systems and optical systems in order to provide a parallel computational base to the applications such as speech or motion recognition and understanding being developed in the Novel Functions field.
This figure outlines our research results showing what has been developed and the relationship between those developments (Fig. 1). Although this figure does not cover all the results, it conveys the main points.
Fig. 1
In the Massively Parallel Systems field, we have conducted research and development of computer architecture, system software, and applications.
Regarding Computer Architectures, we have developed parallel machines as RWC-1, EM-X, SOP, and a parallel secondary storage system PDM.
In the System Software area, we conducted research into and development of programming models, languages, compilers, and operating systems for easy and effective use of massively parallel systems. We developed an SCore operating system; R-DB, R-ET, and R-PF programming environment products; and Ocore, PROMOTER, MPC++, UFO, and PF90 programming languages.
We have been also working on a discrete event simulation environment, OSim, and a protein structure prediction system, ODA, as parallel applications.
The key technologies we have focused on in our research and development are shown in this figure (Fig. 2).
Fig. 2
Regarding Computer Architectures, we concentrated our efforts on the development of a general-purpose massively parallel system in the sense that a variety of execution models is supported. We have also studied on an architecture for the future device technology.
In the Programming Models and Languages field, we have been working on language support for massively parallel programming based on object-oriented techniques.
Since the compiler technology is very important, we have also been working on a compiler technology for generating optimization codes on massively parallel systems as well as the development of programming languages.
The operating system is important basic software which manages the resources of massively parallel computers. Conventionally, massively parallel computers were used for so-called number crunching problems by a limited number of specialists. Thus, any operating system on a massively parallel computer was difficult to use for non-specialists. We put our efforts into developing an operating system for massively parallel computers that would provide an easy-to-use, interactive, and multi-user environment on your desktop for your daily research or business uses.
We have also attempted to pioneer new application areas for massively parallel systems.
Now, I would like to present the outline of the current research activities and achievements (Fig. 3).
Fig. 3
Regarding Computer Architectures, the Massively Parallel Architecture Lab. at TRC conducted the research and development of the massively parallel computer, RWC-1. The RWC-1 provides an architectural support for implementing Fine Grain Parallel Execution and OS functions. ETL is conducting the research and development of the EM-X. This is also a parallel computer primarily for Fine Grain Parallel Execution. The Massively Parallel NEC Lab. has developed a reconfigurable parallel computer, SOP, based on FPGA technology. The Massively Parallel Sanyo Lab. has conducted the research and development of the Parallel Disk Module (PDM).
Continuing, I would like to report on the current research activities and achievements in the System Software field; including an operating system, programming environment, language, and compiler (Fig. 4).
Fig. 4
The Massively Parallel Software Lab at TRC conducted the research and development of OCore and MPC++ programming languages. OCore established a programming model which supports massively parallel programming based on the Concurrent Object-Oriented Programming Model. MPC++ is a programming language developed for system programming on the RWC-1 and other parallel computers.
The Massively Parallel GMD Lab. conducted the development of the programming model and language, PROMOTER. PROMOTER has high-level abstract functions which can define distributed data types useful for application descriptions.
One of our subcontracted universities, the University of Manchester, has designed UFO, a language combining object-oriented and functional programming; and implemented its compiler system.
The Massively Parallel MRI (Mitsubishi Research Institute) Lab. has developed software such as debugger, tracer, and profiler as programming environments.
The Massively Parallel Software Lab. at TRC has conducted the research and development of a scalable operating system, SCore, which can effectively work on massively parallel systems.
In addition, ETL has been working on the GVVM as a virtual address management method on massively parallel systems.
We have also carried out MPS research on application areas other than Novel Functions from the viewpoint of Massively Parallel Systems research (Fig. 5).
Fig. 5
The Massively Parallel Mitsubishi Lab. has studied OSim as a tool for discrete event simulation. Here, discrete event simulation simulates, for example, the behavior of individual vehicles in a car traffic situation. While conventional simulation is based on the queuing model, the current one directly simulates the phenomena.
In the area of protein structure prediction, the Massively Parallel Mitsubishi Lab. and the Massively Parallel NEC Lab. are conducting research on prototype systems. Although this field is still under research and development, once the protein structure can be predicted in a short period of time on a massively parallel system, it will be used for development of new medicines. It is expected that this application will break the recent stagnation in the growth of the massively parallel systems market.
Finally, let's examine our Optical Systems achievements (Fig. 6).
Fig. 6
The basic technology we have attempted to develop in the Optical Systems area is optical interconnection technology. This technology will be applied to chip-to-chip, board-to-board, and cabinet-to-cabinet interconnections for computers. Some application examples include interconnections among neural devices in electronic devices, and interconnections among optical image processors in optical devices.
The problems we try to solve with optical interconnection (Fig. 7) include: the pin bottleneck, caused by the limit in the number of electrodes which can be mounted on a chip or a board; the wire-mass, that is the difficulty of installation and maintenance of computers due to the volume of a great number of cables drawn out from a board or a cabinet; the difficulty in transmitting information to locations more than several meters away when the amount of information passing through wires from a board or a cabinet increases; the complexity of and interference among wires when a great number of wires pass among microdevices; and the overall information transmission throughput inside and outside of computers when it reaches the upper limit of its capabilities.
Fig. 7
To implement optical interconnection for computers, technology with the following characteristics must be developed (Fig. 8).
Fig. 8
First, a low cost technology. To implement this, a laser with a structure that effectively increases production yield must be developed. Also, a laser with a structure which effectively increases the uniformity of an array, and a package structure which fits mass production is required.
Second, a high-speed and highly reliable technology. For this technology, it is necessary to develop a laser which can operate under high temperatures, and a low-threshold, array type, laser with uniform oscillation delay.
Third, we need an easy-to-handle technology. By this, I mean that we have to develop a compact package, and a laser with low power consumption and a low oscillation threshold.
Currently, the following technologies are being developed (Fig. 9).
Fig. 9
The technology for chip-to-chip interconnection is being developed by Oki and Fujikura. The technology for board-to-board interconnection is being pursued by NEC, Hitachi, and Sumitomo Electric. The technology for optical interconnection devices is being developed by Sanyo, Toshiba, Nippon Sheet Glass, Fujitsu, and Furukawa Electric. A neural chip is developed by Mitsubishi. The technology for image processing devices is being developed by Matsushita.
The following are some examples of our research achievements in the optical systems research field (Fig. 10).
Fig. 10
These include the direct bonding of Inp on Si substrate at 400 degrees; the demonstration of board-to-board optical interconnection at 4.8Gbps; the prototyping of a two-dimensional OEIC receiver array with 256 channels with an address selection function; the continuous wave operation of 1.3 u m surface-light-emitting laser at 36 degrees; the continuous wave operation of GaInNAs laser diode at room temperature; and finally the prototyping of an optical neural chip with 128 elements. I have briefly explained the achievements of the Massively Parallel and Optical Systems during the first five years of our project. Finally, many of you may have wondered why there are no oral presentations of the Massively Parallel and Optical Systems when looking at the brochure of this Symposium. Allow me to explain (Fig. 11). The Program Committee thought that we cannot present all of the research results in a limited time because they are so great in number. Since the research results of the Massively Parallel Systems and the Optical Systems can be shown as research products, the Proceedings include all of the papers in full, and the presentations of all the results are either at the demonstration site or the poster site.
These demonstrations are planned for later today and tomorrow. Please visit our demonstration site to see what our products actually are and to deepen your understanding.
Fig. 11
Demonstrations of Massively Parallel Systems(ETL)
Poster Presentation of Massively Parallel/Optical Systems
(Front:
Optoelectronics Furukawa Lab.)