| Visitor: |
Mitsuhisa Sato | (TRC Massively Parallel Performance Laboratory) (Computer Architecture Laboratory, Computer Science Division, Electrotechnical Laboratory as of the date of this trip) |
| Period: | February 2 - 11, 1996 | (10 days) |
| Places | (attended conferences): | |
| 1) | Second International Symposium on High-PerformanceComputer Architecture (HPCA-2) | |
| 2) | Workshop on Multithreaded Architecture Stanford University |
I attended the WS on Multithreaded Architecture, jointly held in San Jose, U.S.A., with the Second International Symposium on High-Performance Computer Architecture (HPCA-2) to present our collaborative research with RWCP titled "The Design of MPC++ Runtime for RWC-1 Multiprocessor" and the subsequent discussions.
This workshop is on multithreaded architecture and software such as runtime libraries. My presentation focused on the design policy in the primary phase (hence I could not present a specific evaluation), emphasizing a co-design with architecture.
Then, I attended HPCA-2 to investigate computer architectures, especially parallel architectures. As a trend in symposiums in this field, many presented papers focused on how shared memory models should be supported, and shared memory and workstation clusters attracted much attention. On-chip multiprocessors were also expected due to the recent high performance and integration of processors.
The main topics throughout HPCA-2 and the workshop were "shared memory architecture" and "multithreading."
Shared memory architecture is a recent trend and its potential appears to be great, as revealed by the acceptance of SMP in the market and its continuity. However, because most on the shared memory architecture in hardware terms may have been already presented, more software-oriented research projects toward SVM (shared virtual memory) using paging hardware and workstation clusters are starting to flourish. For instance, the Telegraphos Project in Greece and SHRIMP in Princeton University were presented at HPCA.
Multithreading has been studied for several years and research on it is now booming because multitask processing with multithreading is becoming more realistic on recent workstations of SMP. In particular, studies are being conducted on implementing multiprocessors on a single chip as integration of multiprocessors increases, and so studies on improved efficiency with multithreading will be stepped up.
I visited the Stanford University group led by Professor Anoop Gupta to investigate trends in parallel processors, and introduced EM-X developed in our laboratory. I also listened to their explanation on FLASH, a shared memory multiprocessor developed by Stanford University, and discuss the systems with them. Although they expressed interest in the EM-X architecture, the discussions were not detailed to my regret, because it was far-removed from their project which uses general-purpose processors.
Like the research works presented at HPCA, I was interested in research leading to future technologies and research focusing on reducing costs for high-performance PCs and workstations. They said they planned to use OLTP (On-line Transaction Processing) of databases in addition to scientific computations as application benchmarks. I felt that it was a very American orientation, maybe taking into account the recent economic situation of MPP and the multiprocessor market.