Kei Hiraki

Professor Graduate School University of Tokyo

Profile

Affiliation:	Department of Information Science, Division of Science, Graduate School, University of Tokyo
Date of Birth:	September 11, 1951
Place of Birth:	Tokyo
Background:
1976	Graduated from Physics Department, Faculty of Science, University of Tokyo
1982	Completed doctor course in Physics Department, Faculty of Science, Graduate School, University of Tokyo
1982	Joined Electrotechnical Laboratory, Agency of Industrial Science and Technology, MITI
1988-1990	Visiting researcher at T.J. Watson Research Center of IBM in U.S.A.
1991	Department of Information Science, Division of Science, Graduate School, University of Tokyo
Hobbies:	I have many hobbies; to name a few: music (playing, listening, and making instruments), cycling, and travel. Building computers, my profession, could be added to this list of specialties.

Outlines of Research in RWC and Future Plan

Few would deny that parallel and distributed computing is the future mode of computing. 15 years ago it was pointed out that a system with 128 constituent processors had only 30% efficiency at most, or that estimation was too optimistic, and that parallel processing for general computing was impossible. I think that those days were in a totally different age.

There are various reasons for this, especially non-scientific aspects such as the unlimited requirement for computing power, the limited increase of computing power with conventional methods, rapidly falling costs of computers, accumulation of legacy software written by dedicated programmers, and the familiarity of parallel computers. In addition, there were the following important technological and architectural developments:

• Establishment of data flow method both in architecture and compiler
• Apparent parallelism utilization, dissemination of parallel software, and high-speed and low-latency data communication technology
• Establishment and dissemination of snoop method in bus-linked computers The former is an approach to implementation of parallel computing with correct results, and the latter is an approach to efficient implementation of interprocessor communication.

To make parallel processing accessible to anybody for more general purposes in the future, it might be necessary to further advance the above direction and to retain continuity with the current mainstream computing systems to implement distributed and parallel computing systems that are fully scalable.

With this perspective, my laboratory is conducting research on software, architecture, and hardware with the goal of creating a general-purpose massively parallel computing system with distributed implementation. The core of this research is the efficient implementation of a shared memory method on a scale that exceeds the scope possible with bus linking, that is, to develop a general-purpose, efficient distributed shared memory method.

The distributed shared memory method itself has a long history and many prototype systems have been built, some of them commercial. However, most of those distributed shared memory systems are still far from the above goal because (1) they are incompatible with a parallel computing model in which they communicate with each other, or (2) they are incapable of practical computation due to bottlenecks of network bandwidth or latency.

Our research theme in RWC reflects the above issues. That is, the goal of "research on a distributed shared memory method in massively parallel systems" was set to resolve the problem of the conventional distributed shared memory method, which is difficult to apply to the fine-grain massively parallel processing method, by combining "synchronization" and "sharing" and to establish a distributed shared memory method, which uniformly and efficiently handles data parallel message passing and data-driven operations. It may be too abstract, so a brief yet specific explanation is given below. It is of course necessary to develop a correct method and implement it on a high-performance, low-priced system when this parallel processing method based on distributed shared memory is to be practical, but it is also essential to increase the pool of experience and theory by creating: (1) a sufficiently general, high-performance memory model, and (2) a pilot model to demonstrate its feasibility.

We started from integrating synchronization and shared protocols and completed our first pilot model "Ochanomizu I". The relationship between synchronization/sharing and interlinked networks in this model required clarification, so we focused on a generalized combining capability and are now demonstrating it on our second pilot model "Ochanomizu V". Another insight gained from the first pilot model was the adverse effect on efficiency of synchronization latency caused by sharing, and this will become more severe in future distributed parallel processing. We therefore proposed an elastic memory consistency model which is currently being evaluated.

In future, we will create a demonstrational prototype using the distributed shared memory method which has been clarified in our research and verify this prototype, including system software and application programs.